The business question here is basically “who is correctly priced for volatility?” A GPU is long volatility on AI workloads. You pay a huge generality tax, but you’re protected if tomorrow’s models need different precision, routing, kernels, memory access, batching behavior, etc. An ASIC is short volatility. You win if the workload stabilizes, and you get destroyed if the frontier moves before your tape-out pays back.
volta tensor cores weren't systolic arrays! There's heavy evidence they were tree-adders (https://arxiv.org/abs/1811.08309) && afaik only Blackwell TCs are obviously systolics by documentation
The chalkboard format on this kind of material is the right tradeoff. Most chip coverage stays one layer up, at "TPU versus GPU" or "ASIC versus general-purpose," and skips the multiply-accumulate primitives that actually determine why the SKUs look different. The MatX framing is the interesting one, since the merchant-silicon thesis is a bet that hyperscaler in-house chips like TPU, Trainium, and Maia leave room for a third lane between Nvidia and the captive accelerators. Whether that lane exists at scale is the production question over the next two earnings cycles.
The third lane question usually gets framed as whether MatX can out-engineer Nvidia, but the merchant-silicon bet is really about TSMC allocation. When OpenAI's CPU demand alone has TSMC unable to meet 80% of orders and prices rising 50%, the binding constraint on a third lane isn't architecture, it's whether you can buy wafers behind Nvidia and three hyperscalers already holding capacity contracts.
The business question here is basically “who is correctly priced for volatility?” A GPU is long volatility on AI workloads. You pay a huge generality tax, but you’re protected if tomorrow’s models need different precision, routing, kernels, memory access, batching behavior, etc. An ASIC is short volatility. You win if the workload stabilizes, and you get destroyed if the frontier moves before your tape-out pays back.
volta tensor cores weren't systolic arrays! There's heavy evidence they were tree-adders (https://arxiv.org/abs/1811.08309) && afaik only Blackwell TCs are obviously systolics by documentation
Have the winners for the blog prize been chosen yet?
Didn't really like this.
I love that “informing…inspiring” is formed to replace a threat.
“You cannot meet the demands, so get in line!”
This is the “hedge and ditch” rule in action but without a law to back it.
How to own the Wild West – White American style (so utilising the help of bought and graded-humans)
The chalkboard format on this kind of material is the right tradeoff. Most chip coverage stays one layer up, at "TPU versus GPU" or "ASIC versus general-purpose," and skips the multiply-accumulate primitives that actually determine why the SKUs look different. The MatX framing is the interesting one, since the merchant-silicon thesis is a bet that hyperscaler in-house chips like TPU, Trainium, and Maia leave room for a third lane between Nvidia and the captive accelerators. Whether that lane exists at scale is the production question over the next two earnings cycles.
The third lane question usually gets framed as whether MatX can out-engineer Nvidia, but the merchant-silicon bet is really about TSMC allocation. When OpenAI's CPU demand alone has TSMC unable to meet 80% of orders and prices rising 50%, the binding constraint on a third lane isn't architecture, it's whether you can buy wafers behind Nvidia and three hyperscalers already holding capacity contracts.